Data converters are provided for receiving either an analog signal for conversion to a digital signal or a digital signal for conversion to analog signal. For conversion of analog signals to digital signals, an analog-to-digital converter is utilized. This is typically facilitated by sampling an analog voltage onto a capacitor array having a plurality of binary weighted capacitors. The capacitors then have the ability to have one plate thereof selectively switched between a reference voltage and ground to redistribute the charge among the capacitors, the switching done in a sequential manner in accordance with a successive approximation algorithm. By selectively switching the plates of the capacitors, and comparing the other plate of the capacitors, which is connected to a common input of a comparator, to a reference voltage, a digital value for the analog voltage sampled at the input can be determined.
A number of problems exist with the data conversion of an analog signal to a digital signal. Some of these problems reside in the various offsets of the inputs to the comparators, one of which is due to the fact that the actual chip ground may be different from the input ground at the PC board on which the actual chip is disposed. Additionally, the capacitors in the capacitor array are weighted and can have errors associated therewith. These errors can be accounted for by actually calibrating each of the capacitors with a sub-capacitor array. However, this calibration must be done at each power up of the A/D convertor. Additionally, these capacitor arrays can also have various parasitics associated therewith that effect the operation thereof and require the driving voltage to drive a higher capacitance value than that associated with the capacitance array.
When the capacitor arrays are operated in accordance with a data conversion algorithm such as a SAR algorithm, during the sampling period, the output node of the capacitor array is typically connected to an input of an amplifier and that input connected to a reference voltage. When operating in conjunction with a differential input amplifier, typically both input nodes thereof are switched to a common mode voltage during the sampling or tracking phase where the input voltage is impressed across the switched capacitors and then switched to the capacitor array thereafter. However, it is important when operating with a single array that noise introduction by the voltage source driving the common mode node or reference node for each of the inputs is cancelled. Unless these are balanced, there will be a noise contribution due to this reference voltage circuit.
During the sampling operation in a SAR data converter, a capacitor array will have an input voltage sampling thereacross. This requires the input to the SAR converter, this typically being an analog input to the integrated circuit associated therewith, is required to drive one plate of all the capacitors in the array that are connected thereto. However, when capacitors are fabricated, they are typically comprised of two plates disposed above the surface of the substrate, these plates typically fabricated from polycrystalline silicon separated by a dielectric. However, the lower one of these plates is typically separated from the surface of the substrate by a dielectric. This lower plate is therefore capacitively coupled to the substrate, which is also conductive. This results in a parasitic capacitor. Therefore, in addition to charging up each of the capacitors from the input pin, each of the parasitic capacitors also has to be charged up. Since the parasitic capacitor is connected to ground, this will not affect any subsequent sampling operation. However, it does require a not insignificant amount of current to be provided for the purpose of charging up the parasitic capacitors.